Hawk
SoC Architecture
20+ years in IC. Deputy Chief Engineer, Technical Director, CTO & Deputy GM of an automotive BU. Core contributor to HiSilicon Kirin AI IP.
NoorTech Malaysia Sdn. Bhd. · Malaysia
Let AI Bring Machines to Life
A Malaysian chip company designing high-compute SoCs for vehicles, robots, the cloud and aerospace, with self-developed NPU IP, an in-house compiler, and an advanced packaging and test capability growing alongside.
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What we do
01 Wholly owned
Computing chip design
Our core business. High, mid and low-end computing chips built on self-developed NPU core IP, with full SoC architecture and system verification held in-house rather than outsourced.
02 Joint venture
Automotive chip testing
A joint venture developing vehicle-grade test capability alongside the products it qualifies, closing the loop between design and certification instead of waiting on third parties.
03 Joint venture
Advanced packaging
A strategic footprint in 2.5D and 3D packaging, the capability that increasingly decides how much performance a design can actually deliver.
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The integrated platform
Hardware
“Depth” NPU subsystem
A ring-bus computing architecture keeping compute, memory and host processor close together, so utilisation holds up on real workloads rather than only on benchmark kernels.
Software
“Ladder” compiler
An integrated RISC-V and NPU compiler: graph optimisation, operator fusion and instruction scheduling, the last mile that lets existing models run on our silicon without teams changing how they work.
Discipline
Automotive-grade flow
The full development flow runs to ISO 9001, and automotive products are developed to conform to ISO 26262. The bar that earns a place in a vehicle.
Company
Building a world-leading computing-chip cluster, from Malaysia outward.
Incorporated in April 2026 with RM 10,000,000 in registered capital, NoorTech is rooted in automotive compute and reaching globally, with R&D centres being established in China, North America, Europe and Japan, and joint ventures forming in packaging and test.
- Incorporated
- 2026
- Registered capital
- RM 10,000,000
- Headquarters
- Malaysia
- R&D centres, in registration
- Four regions
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Leadership
Jason
NPU Architecture
Former AI chief expert at Huawei Smart Engineering. Lead architect on a first-generation cloud LLM inference chip. Former NPU architect at Qualcomm and NIO.
Oliver
NPU Compiler
PhD in compilation, Chinese Academy of Sciences. Led NPU architecture for a high-compute ADAS chip at sparse INT8 above 1000T.
Steven
SoC Design
15 years and 10+ mass-production chip programmes. Most recently responsible for cloud-side high-compute SoC architecture and design.
James
Software Solutions
20 years in chip system software across multimedia and AI, spanning edge-side and cloud-side high-compute inference.
Zora
Hardware Solutions
16 years in post-silicon test and hardware architecture. Automotive-grade certification across multiple vehicle-grade chips.
Contact
Let AI Bring Machines to Life
Partners, investors and engineers: we would like to hear from you.